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LCK4993YH-DT Datasheet(PDF) 6 Page - Agere Systems |
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LCK4993YH-DT Datasheet(HTML) 6 Page - Agere Systems |
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6 / 25 page  LCK4993/LCK4994 Data Sheet, Revision 1 Low-Voltage PLL Clock Drivers May 5, 2004 6 6 Agere Systems Inc. 72 REFSEL LVTTL Id Reference Input Select. The REFSEL input controls how the reference input is configured. Low = REFSEL uses the REFA pair as the reference input. High = REFSEL uses the REFB pair as the reference input. 77, 78, 80, 81 FBKA+, FBKA–, FBKB–, FBKB+ LVTTL/ LVDIFF I Feedback Inputs. One pair of inputs selected by the FBSEL is used to feedback the clock output xQn to the phase detector. The PLL will operate so that the rising edges of the reference and feedback signals are aligned in both phase and frequency. These inputs can operate as differential PECL or single-ended TTL inputs. When operating as a single-ended LVTTL input, the complementary input must be left open. 79 FBSEL LVTTL Id Feedback Input Select. Low = FBKA inputs are selected. High = FBKB inputs are selected. 84, 86 QFA[0:1] LVTTL O Clock Feedback Output. This pair of clock outputs is intended to be connected to the FB input. These outputs have numerous divide options and three choices of phase adjustments. The function is determined by setting the FBDS[0:1] pins and FBF0. 98, 99 FBDS[0:1] 3-Level Input I Feedback Divider Function Select. These inputs determine the function of the QFA0 and QFA1 outputs, see Table 5-4. 100 LOCK LVTTL O PLL Lock Indicator. Low = the PLL is attempting to acquire lock. High = this output indicates the internal PLL is locked to the ref- erence signal. Note: I d = each input has an internal pull-down resistor. Table 4-2. 100-Pin TQFP Descriptions (continued) Pin Symbol Type I/O Description |
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