TFRA84J13 Ultraframer

Product Description, Revision 4

DS3/E3/DS2/E2/DS1/E1/DS0

April 29, 2005

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Agere Systems Inc..

1 Introduction .........................................................................................................................................................................1

2 Features .............................................................................................................................................................................3

2.1 Test Pattern Generator/Monitor (TPG/TPM) (x1) ........................................................................................................3

2.2 M13/E13 MUX (x3) ......................................................................................................................................................3

2.2.1 M13 ....................................................................................................................................................................3

2.2.2 E13 .....................................................................................................................................................................3

2.3 DS1/J1/E1 Framing (FRM) (3x28/21) ..........................................................................................................................4

2.4 DS3/E3/DS2/E2/DS1/E1 Multirate Cross Connect (MRXC) (x1) .................................................................................4

2.5 DS1/E1 Digital Jitter Attenuation (DJA) (3x28/21) .......................................................................................................5

2.6 Microprocessor Unit (MPU) (x1) ..................................................................................................................................5

2.7 JTAG ...........................................................................................................................................................................5

3 Overview .............................................................................................................................................................................6

4 Application Diagrams ..........................................................................................................................................................7

4.1 DS3/E3 to/from DS1/E1 Application ............................................................................................................................7

4.2 DS3/E3 to/from DS0/E0 Application ............................................................................................................................8

4.3 DS1/E1 to/from DS0/E0 Application ............................................................................................................................9

5 Block Description ..............................................................................................................................................................10

5.1 M13/E13 Multiplexer (M13/E13 MUX) .......................................................................................................................10

5.1.1 M13 MUX .........................................................................................................................................................10

5.1.1.1 Receive Direction ..................................................................................................................................10

5.1.1.2 Transmit Direction .................................................................................................................................10

5.1.2 E13 MUX ..........................................................................................................................................................10

5.2 Multirate Cross Connect (MRXC) ..............................................................................................................................11

5.3 DS1 Digital Jitter Attenuator (DS1/E1 DJA) ...............................................................................................................11

5.4 Test Pattern Generator/Monitor (TPG/TPM) .............................................................................................................11

5.5 Clock Generator (CG) ................................................................................................................................................12

5.6 Framer (FRM) ............................................................................................................................................................12

5.6.1 Line Decoder/Encoder .....................................................................................................................................12

5.6.2 Receive Frame Aligner/Transmit Frame Formatter ..........................................................................................12

5.6.3 Receive Performance Monitor ..........................................................................................................................12

5.6.4 Signaling Processor .........................................................................................................................................13

5.6.5 Facility Data Link (FDL) Processor ..................................................................................................................13

5.6.6 HDLC Unit ........................................................................................................................................................13

6 Glossary ...........................................................................................................................................................................14