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TFRA84J13DS1 Datasheet(PDF) 9 Page - Agere Systems |
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TFRA84J13DS1 Datasheet(HTML) 9 Page - Agere Systems |
9 / 14 page Product Description, Revision 4 TFRA84J13 Ultraframer April 29, 2005 DS3/E3/DS2/E2/DS1/E1/DS0 Agere Systems Inc. 9 4.3 DS1/E1 to/from DS0/E0 Application 2016 DS0/E0s are input from a switch, DS1/E1 framed, and output to 84 DS1/63 E3 LIUs. Similarly, 84 DS1s/63 E1s are input from the LIUs, deMUXed, and output as 2016 DS0s/E0s. The DS1s/E1s will be received/transmitted by the device via the LINERX/TXDATA pins. The DS0s/E0s will be received/transmitted by the device via the CHIRX/TXDATA pins. The system interface can be the CHI (concentrated highway interface) or PSB (parallel system bus): — CHI can be programmed to operate at 8.192 MHz or 16.384 MHz clock and data rates. — The PSB interface consists of a 16-bit wide parallel bus operating at 19.44 Mbits/s. All three instances of the 28/21 channel framers are configured identically for switching mode (DS1/E1 to/from DS0/E0) of operation. DS1/E1 level performance monitoring capabilities on all channels in the Rx direction (DS1/E1 to DS0/E0) of the signal path. Figure 4-3. 84 DS1s/63 E1s to/from 2016 DS0s/E0s Configuration SYSTEM INTERFACE (CHI OR PSB) ULTRAFRAMER DS1/E1 (2016) DS0/E0 84/63 SWITCH CLK GEN TSWC01622 REF CLK DS1/E1 LIU |
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