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MX23L3254MC-20 Datasheet(PDF) 7 Page - Macronix International

Part # MX23L3254MC-20
Description  32M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface
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Manufacturer  MCNIX [Macronix International]
Direct Link  http://www.macronix.com
Logo MCNIX - Macronix International

MX23L3254MC-20 Datasheet(HTML) 7 Page - Macronix International

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P/N: PM1167
REV. 1.2, JUN. 08, 2005
MX23L3254
Figure 4. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S#) Low.
The instruction code for the Read Data Bytes (READ)
instruction is followed by a 3-byte address (A23-A0), each
bit being latched-in during the rising edge of Serial Clock
(C). Then the memory contents, at that address, is shifted
out on Serial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 4. The first
byte addressed can be at any location. The address is
automatically incremented to the next higher address after
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ)
instruction.When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by
driving Chip Select (S#) High. Chip Select (S#) can be
driven High at any time during data output.
Note: 1. Address bits A23,A22 is Don't Care.
C
D
S#
Q
23
2
1
3456789 10
28 29 30 31 32 33 34 35
22 21
3210
36 37 38
76543
1
7
0
High Impedance
Data Out 1
Instruction
24-Bit Address
0
MSB
MSB
2
39
Data Out 2


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