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HT48R07A-1 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT48R07A-1 Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 37 page  HT48R07A-1 Rev. 1.00 11 March 13, 2006 after the dummy period is finished. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: · RES reset during normal operation · RES reset during HALT · WDT time-out reset during normal operation The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re - set ² that resets only the Program Counter and SP, leav- ing the other circuits in their original state. Some regis- ters remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets². TO PDF RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: ²u² means ²unchanged² To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys- tem reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack W a r m R e s e t W D T H A L T C o l d R e s e t R E S S y s t e m R e s e t S S T 1 0 - b i t R i p p l e C o u n t e r O S C 1 Reset Configuration R E S V D D 1 0 0 k W 1 0 k W 0 . 1 m F * 0 . 0 1 m F * Reset Circuit Note: ²*² Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. t S S T R E S V D D S S T T i m e - o u t C h i p R e s e t Reset Timing Chart |
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