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PI74SSTU32864 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI74SSTU32864 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 10 page  1 PS8636B 07/26/04 Features • PI74 SSTU32864 is designed for low-voltage operation, VDD = 1.8V • Supports Low Power Standby Operation • All Inputs are SSTL_18 Compatible, except RST, C0, C1, which are LVCMOS. • Output drivers are optimized to drive DDR-II DIMM loads • Designed for DDR Memory • Packaging (Pb-free & Green available): -96 Ball LFBGA (NB) Block Diagram 1:2 Mode (Positive Logic) PI74SSTU32864 25-Bit 1:1 or 14-Bit 1:2 Configurable Registered Buffer TO OTHER CHANNELS CK CK RST 1D C1 R QCKEA QCKEB* QODTA 1D C1 R Q1A Q1B* QCSB* QCSA 1D C1 R 1D C1 R QODTB* VREF DCKE DODT DCS CSR D1 Note: Disabled in 1:1 configuration 0 1 Description PericomSemiconductor’sPI74SSTU32864logiccircuitisproduced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V LVCMOS drivers that have been optimized to drive the DDR-II DIMM load. The SSTU32864 operates from a differential clock (CK and CK). Data is registered at the crossing of CK going high, and CK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration for 25-Bit 1:1 (when LOW) to 14-Bit 1:2 (when HIGH). The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up. IntheDDR-IIRDIMMapplication,RSTisspecifiedtobecompletely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will functionnormally.TheRSTinputhaspriorityovertheDCSandCSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs. |
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