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552DE622M080BGR Datasheet(PDF) 2 Page - Silicon Laboratories |
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552DE622M080BGR Datasheet(HTML) 2 Page - Silicon Laboratories |
2 / 8 page Si552 2 Preliminary Rev. 0.2 1. Electrical Specifications Table 1. Si552 Electrical Specifications Parameter Min Typ Max Units Notes Frequency Nominal Frequency LVDS/CML/LVPECL CMOS 10 10 — — 945 160 MHz Specified at time of order by P/N. Also available in bands from 970 to 1134 MHz and 1213 to 1417 MHz. Initial Accuracy –1.5 — 1.5 ppm Measured at +25 °C at time of ship- ping and at VC = VDD/2. Temperature Stability –20 –50 –100 — — — +20 +50 +100 ppm Selectable option by P/N. See Section 4. "Ordering Information" on page 7. Measured at VC =VDD/2. Linearity BSL Incremental –5 –10 ±1 ±5 +5 +10 % BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope determined with VC ranging from 10 to 90% of VDD. Tuning Slope (kV) from 10 to 90% of VDD — — — 180 90 45 — — — ppm/V Positive slope; selectable option by P/N. See Section 4. "Ordering Infor- mation" on page 7. Modulation Bandwidth — 10 — kHz VC Input Impedance 500 — — k Ω Absolute Pull Range (APR) — See Notes — — See Section 4. "Ordering Information" on page 7. Aging — — ±10 ppm Projected frequency drift over 15 year life. Outputs Symmetry 45 — 55 % LVPECL: VDD – 1.3 V (differential) LVDS: 1.25 V (differential) CMOS: VDD/2 RMS Jitter for FOUT > 500 MHz Kv = 180 ppm/V 12 kHz to 20 MHz 50 kHz to 80 MHz Kv = 45, 90 ppm/V 12 kHz to 20 MHz 50 kHz to 80 MHz — — — — 0.42 0.34 0.28 0.31 — — — — ps FOUT > 500 MHz Differential Modes: LVPECL/LVDS/CML |
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