Si550

Preliminary Rev. 0.3

5

Table 6. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Period Jitter*

RMS

—

2

—

ps

Peak-to-Peak

—

14

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.

Table 7. CLK± Output Phase Noise (Typical)

Configuration

Output

74.25 MHz

45 ppm/V

CMOS

300 MHz

90 ppm/V

LVPECL

622.08 MHz

45 ppm/V

LVPECL

Units

Offest Frequency (f)

100 Hz

1kHz

10 kHz

100 kHz

1MHz

10 MHz

100 MHz

L (f)

dBc/Hz

–94

–117

–128

–135

–138

–143

n/a

–74

–98

–112

–122

–134

–144

–147

–77

–101

–114

–118

–128

–144

–147