Si530/531

Preliminary Rev. 0.4

3

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

mid-level

—

V

swing (diff)

1.1

—

1.9

swing (single-ended)

0.5

—

0.93

mid-level

1.125

1.20

1.275

V

swing (diff)

0.32

0.40

0.50

mid-level

—

—

V

swing (diff)

0.70

0.95

1.20

—

V

—

—

0.4

Rise/Fall time (20/80%)

LVPECL/LVDS/CML

—

—

350

ps

CMOS with CL = 15 pF

—

1

—

ns

Symmetry (duty cycle)

SYM

LVPECL:

LVDS:

1.25 V (diff)

CMOS:

45

—

55

%

Notes:

1. 50

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Phase Jitter (RMS)*

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

—

—

0.27

0.30

—

—

ps

Phase Jitter (RMS)*

φ

J

12 kHz to 20 MHz (OC-48)

—

0.50

—

ps

*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.

Table 5. CLK± Output Period Jitter

Parameter

Symbol

Test Condition

Min

Typ

Max

Units

Period Jitter*

RMS

—

1

—

ps

Peak-to-Peak

—

5

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.