MX26LV160BMC-70G datasheet(11/48 Pages) MCNIX

Part #	MX26LV160BMC-70G

Description	16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY BOOT SECTOR HIGH SPEED eLiteFlashTM MEMORY

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Manufacturer	MCNIX [Macronix International]

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11

P/N:PM1090

MX26LV160

REV. 1.0, NOV. 08, 2004

nal reset operation is complete, which requires a time of

tREADY (during Embedded Algorithms).The system can

thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms). The sys-

tem can read data tRH after the RESET# pin returns to

VIH.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID READ COMMAND

High speed Flash memories are intended for use in ap-

plications where the local CPU alters memory contents.

As such, manufacturer and device codes must be ac-

cessible while the device resides in the target system.

PROM programmers typically access signature codes

by raising A9 to a high voltage (VID). However, multi-

plexing high voltage onto address lines is not generally

desired system design practice.

The MX26LV160 contains a Silicon-ID-Read operation to

supple traditional PROM programming methodology. The

operation is initiated by writing the read silicon ID com-

mand sequence into the command register.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H or

sector erase command 30H.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1" (see Table 7), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

last WE# or CE# pulse, whichever happens first in the

command sequence and terminates when the data on

Q7 is "1" at which time the device returns to the Read

mode, or the data on Q6 stops toggling for two consecu-

tive read cycles at which time the device returns to the

Read mode.

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MX26LV160BMC-70G Datasheet(PDF) 11 Page - Macronix International

MX26LV160BMC-70G Datasheet(HTML) 11 Page - Macronix International

Similar Part No. - MX26LV160BMC-70G

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