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MX28F640C3BXAC-12 Datasheet(PDF) 10 Page - Macronix International |
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MX28F640C3BXAC-12 Datasheet(HTML) 10 Page - Macronix International |
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10 / 44 page  10 P/N:PM0900 MX28F640C3T/B REV. 0.6, AUG. 20, 2003 2 PRINCIPLES OF OPERATION The product includes an on-chip WSM to manage sec- tor erase, word write and lock-bit configuration functions. After initial device power-up or return from reset mode (see section on Bus Operations), the device defaults to read array mode. Manipulation of external memory con- trol pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. All functions associated with altering memory contents-sec- tor erase, word write, sector lock/unlock, status and iden- tifier codes - are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the sector erase, word write and sector lock/unlock.The internal algorithms are regulated by the WSM, including pulse repetition, internal verifica- tion and margining of data. Addresses and data are in- ternally latched during write cycles. Address is latched at falling edge of CE and data latched at rising edge of WE.Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. Interface software that initiates and polls progress of sector erase, full chip erase, word write and sector lock/ unlock can be stored in any sector. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Sector erase sus- pend allows system software to suspend a sector erase to read/write data from/to sectors other than that which is suspend. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location. With the mechanism of sector lock, memory contents cannot be altered due to noise or unwanted operation. When RESET=VIH and VCC<VLKO (lockout voltage), any data write alteration can be failure. During read op- eration, if write VPP voltage is below VPPLK, then hard- ware level data protection is achieved. With CUI's two- step command sequence sector erase, word write or sector lock/unlock, software level data protection is achieved also. 3 BUS OPERATION The local CPU reads and writes flash memory in-sys- tem. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any sector, configuration codes or status register independent of the VPP volt- age. RESET can be at VIH. The first task is to write the appropriate read mode com- mand (Read Array, Read Configuration, Read Query or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset mode, the device auto- matically resets to read array mode. In order to read data, control pins set for CE, OE, WE, RESET and WP must be driven to active. CE and OE must be active to obtain data at the outputs. CE is the device selection control. OE is the data output (Q0-Q15) control and ac- tive drives the selected memory data onto the I/O bus, WE must be VIH, RESET must be VIH, WP must be at VIL or VIH. 3.2 Output Disable With OE at a logic-high level (VIH), the device outputs are disabled. Output pins (Q0-Q15) are placed in a high- impedance state. 3.3 Standby CE at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. Q0~Q15 outputs are placed in a high-im- pedance state independent of OE. If deselected during sector erase, word write or sector lock/unlock, the de- vice continues functioning, and consuming active power until the operation completes. 3.4 Reset As RESET=VIL, it initiates the reset mode. The device enters reset/deep power down mode. However, the data stored in the memory has to be sustained at least 100ns in the read mode before the device becomes deselected |
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