MX29F040CTI-55G datasheet(7/38 Pages) MCNIX

Part #	MX29F040CTI-55G

Description	4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 5V ONLY EQUAL SECTOR FLASH MEMORY

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Manufacturer	MCNIX [Macronix International]

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P/N:PM1201

REV. 1.0, DEC. 20, 2005

MX29F040C

READ/RESET COMMAND

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Microprocessor read cycles retrieve array data. The de-

vice remains enabled for reads until the command regis-

ter contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

The MX29F040C contains a Silicon-ID-Read operation

to supplement traditional PROM programming methodol-

ogy. The operation is initiated by writing the read silicon

ID command sequence into the command register. Fol-

lowing the command wr ite, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of A4H for MX29F040C.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H.

The Automatic Chip Erase does not require the device to

be entirely pre-programmed prior to executing the Auto-

matic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the Read

mode. The system is not required to provide any control

or timing during these operations.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on Q5

is "1"(see Table 4), indicating the erase operation ex-

ceed internal timing limit.

The automatic erase begins on the rising edge of the last

WE# or CE#, whichever happens first pulse in the com-

mand sequence and terminates when the data on Q7 is

"1" and the data on Q6 stops toggling for two consecu-

tive read cycles, at which time the device returns to the

Read mode.

Pins

A0

A1

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Code (Hex)

Manufacture code

VIL

1

0

1

0

C2H

Device code for MX29F040C VIH

VIL

1

0

1

0

1

0

A4H

Sector Protection Verification X

VIH

0

1

01H (Protected)

X

VIH

0

00H(Unprotected)

TABLE 3. EXPANDED SILICON ID CODE

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