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MX29F200CTMI-90G Datasheet(PDF) 8 Page - Macronix International |
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MX29F200CTMI-90G Datasheet(HTML) 8 Page - Macronix International |
8 / 44 page 8 P/N:PM1250 REV. 1.0 , DEC. 14, 2005 MX29F200C T/B READ/RESET COMMAND The read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid command must then be written to place the device in the desired state. SILICON-ID-READ COMMAND Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access signature codes by rais- ing A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system design practice. The MX29F200C T/B contains a Silicon-ID-Read opera- tion to supplement traditional PROM programming meth- odology. The operation is initiated by writing the read silicon ID command sequence into the command regis- ter. Following the command write, a read cycle with A1=VIL,A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of 51H/2251H for MX29F200CT, 57H/2257H for MX29F200CB. SET-UP AUTOMATIC CHIP/SECTOR ERASE COM- MANDS Chip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H. The Automatic Chip Erase does not require the device to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system does not require to provide any control or timing during these operations. When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase-verified command is required). If the Erase operation was unsuccessful, the data on Q5 is "1"(see Table 4), indicating an erase operation exceed internal timing limit. The automatic erase begins on the rising edge of the last WE# pulse in the command sequence and terminates when the data on Q7 is "1" and the data on Q6 stops toggling for two consecutive read cycles, at which time the device returns to the Read mode. Pins A0 A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Code Manufacture code Word VIL VIL 00H 1100 0 0 1 0 00C2H Byte VIL VIL X 1100 0 0 1 0 C2H Device code Word VIH VIL 22H 0101 0 0 0 1 2251H for MX29F200CT Byte VIH VIL X 0101 0 0 0 1 51H Device code Word VIH VIL 22H 0101 0 1 1 1 2257H for MX29F200CB Byte VIH VIL X 0101 0 1 1 1 57H Sector Portection X VIH X 0000 0 0 0 1 01H(Protected) Verification X VIH X 0000 0 0 0 0 00H(Unprotected) TABLE 3. EXPANDED SILICON ID CODE |
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