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HT9172 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT9172 Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
5 / 13 page HT9172 Rev. 1.00 5 March 30, 2006 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 2 3 4 5 6 7 8 9 V D D R T / G T E S T D V D 3 D 2 D 1 D 0 O E V P V N G S V R E F I N H P W D N X 1 X 2 V S S H T 9 1 7 2 0 . 1 m F 3 0 0 k W V D D 3 . 5 7 9 5 4 5 M H z 1 0 0 k W 1 0 0 k W 0 . 1 m F T o n e 2 0 p F 2 0 p F 0 . 1 m F Figure 1. Test Circuit Functional Description Overview The HT9172 tone decoder consists of three band pass filters and two digital decode circuits to convert a DTMF tone into a digital code output. The device contains an operational amplifier to adjust the input signal level as shown in Figure 2. The pre-filter is a band rejection filter which will reject frequencies between 350Hz to 400Hz. The low group filter, filters the low group frequency sig- nal output whereas the high group filter, filters the high group frequency signal output. Each filter output is followed by a zero-crossing detector with incorporates hysteresis. When the signal amplitude at the output exceeds a specified level, it is transferred to a full swing logic signal. When the input signal is recognized as an effective DTMF tone, the DV line will go high, and the corre- sponding DTMF tone code will be generated. Steering Control Circuit The steering control circuit is used to measure the effec- tive signal duration and for protecting against valid sig- nal drop out. This is achieved using an analog delay which is implemented using an external RC time-con- stant, controlled by the output line EST. The timing diagram is shown in Figure 3. The EST pin is normally low and will pull the RT/GT pin low via the ex- ternal RC network. When a valid tone input is detected, the EST pin will go high, which will in turn pull the RT/GT pin high through the RC network. When the voltage on RT/GT rises from 0 to VTRT, which is 2.35V for a 5V power supply, the input signal is effec- tive, and the corresponding code will be generated by the code detector. After D0~D3 have been latched, DV will go high. When the voltage on RT/GT falls from VDD to VTRT, i.e. when there is no input tone, the DV output will go low, and D0~D3 will maintain their present data until a next valid tone input is produced. By selecting suitable external RC values, the minimum acceptable input tone duration, tACC, and the minimum acceptable inter-tone rejection, tIR, can be set. The values of the external RC components, can be chosen using the following formula. Also refer to Figure 5 for details. tACC=tDP+tGTP; tIR=tDA+tGTA; where tACC: Tone duration acceptable time tDP: EST output delay time ( ²L²®²H²) tGTP: Tone present time tIR: Inter-digit pause rejection time ( a ) S t a n d a r d I n p u t C i r c u i t V N G S V R E F C 2 R 2 R 5 ( b ) D i f f e r e n t i a l I n p u t C i r c u i t V P R 4 R 3 C 1 R 1 V i 1 V i 2 V N G S V R E F H T 9 1 7 2 C R 1 R F V P V i H T 9 1 7 2 Figure 2. Amplifier Input Application Circuits |
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