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CTM8B55E Datasheet(PDF) 5 Page - Ceramate Technical |
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CTM8B55E Datasheet(HTML) 5 Page - Ceramate Technical |
5 / 23 page 3.1.5 FSR(File select register pointer): R4 Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the indirect addressing mode shown in Figure 2. 3.1.6 PORT A: R5 PA3:PA0, bi-directional I/O Register 3.1.7 PORT B: R6 PB7:PB0, bi-directional I/O Register 3.1.8 PORT C: R7 PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only 3.1.9 T0MODE REGISTER: T0MODE is a write-only register and the content is listed in Table 2. 3.1.10 IOST (Control Port I/O Mode Register) The IOST register is “write-only” = 0, I/O pin in output mode; = 1, I/O pin in input mode. Bank 3 Bank 2 Bank 1 B7 B6 B5 B4 B3 B2 B1 B0 Indirect Addressing Mode Location Select Read 1 Bank Select FIGURE 2. Data Memory Configuraion 00h INAR 01h Timer0 02h PC 03h STATUS 04h FSR 05h PORT A 06h PORT B 07h PORT C 08h 8 Bytes SRAM 0Fh Bank 0 SRAM 16 Bytes 10h 1Fh 30h 3Fh 50h 5Fh 70h 7Fh Bank 0 CMOS Microcontroller EPROM-Based 8-Bit CTM8B54E/55E/56E/57E * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3529445 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 5 of 23 Rev 1.1 Dec 26,2001 |
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