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CTM8B55E Datasheet(PDF) 9 Page - Ceramate Technical |
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CTM8B55E Datasheet(HTML) 9 Page - Ceramate Technical |
9 / 23 page 3.4 RESET This device may be reset by one of the following ways: (1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after the voltage on MCLR/Vpp pin has reached a logic high level. (2) MCLR reset (normal operation). (3) WDT reset (normal operation). (4) MCLR wake-up (from sleep mode). (5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can be awakened by WDT time-out or reset input on MCLR pin. The contents of registers after reset are listed below: Note: x = unknown, u = unchanged, - = unimplemented, read as “0”, # = refer to the following table Address Register Power-On Reset /MCLR or WDT Reset 00h INAR xxxx xxxx uuuu uuuu 01h Timer0 xxxx xxxx uuuu uuuu 02h PC 1111 1111 1111 1111 03h STATUS 0001 1xxx 000# #uuu 04h FSR 1xxx xxxx 1uuu uuuu 05h PORTA ---- xxxx ---- uuuu 06h PORTB xxxx xxxx uuuu uuuu 07h PORTC xxxx xxxx uuuu uuuu 07h-1Fh General Purpose Register xxxx xxxx uuuu uuuu N/A Acc xxxx xxxx uuuu uuuu N/A IOST 1111 1111 1111 1111 N/A T0MODE --11 1111 --11 1111 Condition Status:bit 4 Status:bit 3 /MCLR Reset (not during SLEEP) u u /MCLR Reset during SLEEP 1 0 WDT Reset (not during SLEEP) 0 1 WDT Reset during SLEEP 0 0 CMOS Microcontroller EPROM-Based 8-Bit CTM8B54E/55E/56E/57E * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C Email: server@ceramate.com.tw Tel:886-3-3529445 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 9 of 23 Rev 1.1 Dec 26,2001 |
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