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M2052 Datasheet(PDF) 5 Page - Integrated Circuit Systems |
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M2052 Datasheet(HTML) 5 Page - Integrated Circuit Systems |
5 / 12 page M2050/51/52 Datasheet Rev 1.0 5 of 12 Revised 23Jun2005 Integ r ated Circuit Systems, Inc. ● Communications Modules ● www.ics t.com ● tel (508) 852-5400 M2050/51/52 SAW PLL FOR 10GBE 64B/66B FEC Preliminar y In f o r m atio n Integrated Circuit Systems, Inc. dividers also control the phase detector frequency. The feedback divider (labeled “Mfin Divider”) provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2051-11-625.0000 (see “Ordering Information” on pg. 12) has a 625.00MHz VCSO frequency: • The de-mapper FEC PLL ratios (in Tables 5 and 6) enable the M2051-11-625.0000 to accept “base” input reference frequencies of: 625.00MHz (“10GbE”), 644.5313 MHz (“10GbE LAN”), and 669.6429MHz (“10GbE 255/238 FEC ”). • The Mfin feedback divider enables the actual input reference clock to be the base input frequency divided by 1, 4, 5, or 25. Therefore, for the base input frequency of 625.00MHz, the actual input reference clock frequencies can be: 625.00, 156.25, 125.00, and 25.00 MHz. (See Table 3 on pg. 3.) The M2050/51/52 includes a Loss of Lock (LOL) indicator, which provides status information to system management software. A Narrow Bandwidth (NBW) control pin is provided as an additional mechanism for adjusting PLL loop bandwidth without affecting the phase detector frequency. Options are available for Hitless Switching (HS) with or without Phase Build-out (PBO). Performance conforms with SONET/ SDH MTIE and TDEV during a reference clock reselection. Allowance for a single-ended input has been facilitated by a unique input resistor bias scheme, which is described next and shown in Figure 4. Input Reference Clocks Two clock reference inputs and a selection mux are provided. Either reference clock input can accept a differential clock signal (such as LVPECL or LVDS) or a single-ended clock input (LVCMOS or LVTTL on the non-inverting input). A single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. For this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal. Configuration of single-ended input has been facilitated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with 50k Ω to Vcc and 50k Ω to ground. The input clock structure, and how it is used with either LVCMOS/LVTTL inputs or a DC- coupled LVPECL clock, is shown in Figure 4. Figure 4: Input Reference Clocks Differential Inputs Differential LVPECL inputs are connected to both reference input pins in the usual manner. The external load termination resistors shown in Figure 4 (the 127 Ω and 82 Ω resistors) is ideally suited for both AC and DC coupled LVPECL reference clock lines. These provide the 50 Ω load termination and the VTT bias voltage. Single-ended Inputs Single-ended inputs (LVCMOS or LVTTL) are connected to the non-inverting reference input pin (DIF_REF0 or DIF_REF1). The inverting reference input pin (nDIF_REF0 or nDIF_REF1) must be left unconnected. In single-ended operation, when the unused inverting input pin (nDIF_REF0 or nDEF_REF1) is left floating (not connected), the input will self-bias at VCC/2. PLL Operation The M2050/51/52 is a complete clock PLL. It uses a phase detector and configurable dividers to synchronize the output of the VCSO with the selected reference clock. The PLL will work correctly, meaning it will phase-lock the VCSO output to the input reference clock, when the internal phase detector inputs are able to run at the same frequency. This means the PLL dividers must be set appropriately and a suitable reference frequency must be chosen for the intended output frequency. When the PLL is not set up appropriately, the VCSO is Key to Device Variants and Look-up Table Options Device Variant Look-up Table Option Mfin Lookup Table is: Mfec Look-up Table is: M2050 Table 3 Table 4 (mapper LUT) M2051 Table 5 (de-mapper LUT) M2052 Table 6 (de-mapper LUT) Table 8: Key to Device Variants and Look-up Table Options MUX 0 REF_SEL 1 VCC 50k 50k VCC 50k 50k LVCMOS/ LVTTL LVPECL 50k 50k VCC 82 127 VCC 82 127 X Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω |
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