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HD667A66R Datasheet(PDF) 10 Page - Hitachi Semiconductor |
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HD667A66R Datasheet(HTML) 10 Page - Hitachi Semiconductor |
10 / 97 page HD66766R Rev. 1.0-1 / September 2002 10 Pin Functions Table 4 Pin Functional Description Signals Number of Pins I/O Connected to Functions IM2-1, IM0/ID 3 I GND or V CC Selects the MPU interface mode: IM2 IM1 IM0/ID0 MPU Interface mode GND GND GND 68 system 16-bit bus interface GND GND Vcc 68 system 8-bit bus interface GND Vcc GND 80 system 16-bit bus interface GND Vcc Vcc 80 system 8-bit bus interface Vcc GND ID Clock synchronized serial interface When a serial interface is selected, the IM0 pin is used as the ID setting for a device code. CS* 1 I MPU Selects the HD66766R: Low: HD66766R is selected and can be accessed High: HD66766R is not selected and cannot be accessed Must be fixed at GND level when not in use. RS 1 I MPU Selects the register. Low: Index/status High: Control For a register or a synchronous clock interface, fixed to the Vcc or GND level. E/WR*/SCL 1 I MPU For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 80-system bus interface, serves as a write strobe signal and writes data at the low level. For a synchronous clock interface, serves as the synchronous clock signal. RW/RD* 1 I MPU For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read For an 80-system bus interface, serves as a read strobe signal and reads data at the low level. For a synchronous clock interface, fixed to the Vcc or GND level. DB0/SDI 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as the serial data input pin (SDI). The input level is read on the rising edge of the SCL signal. DB1/SDO 1 I/O MPU Serves as a 16-bit bi-directional data bus. For an 8-bit bus interface, data transfer uses DB15-DB8; fix unused DB7-DB0 to the Vcc or GND level. For a clock-synchronous serial interface, serves as a serial data output pin (SDO). Successive bit values are output on the falling edge of the SCL signal. |
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