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PA7572J-20 Datasheet(PDF) 4 Page - Anachip Corp |
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PA7572J-20 Datasheet(HTML) 4 Page - Anachip Corp |
4 / 10 page Anachip Corp. www.anachip.com.tw Rev. 1.0 Dec 16, 2004 4/10 Input Cells (INC) Input cells (INC) are included on dedicated input pins. The block diagram of the INC is shown in Figure 6. Each INC consists of a multiplexer and a register/transparent latch, which can be clocked from various sources selected by the global cell (see Figure 7). The register is rising edge clocked. The latch is transparent when the clock is high and latched on the clock’s falling edge. The register/ latch can also be bypassed for a non-registered input. I/O Cell (IOC) All PEEL™ Arrays have I/O cells (IOC) as shown above in Figure 6. Inputs to the IOCs can be fed from any of the LCCs in the array. Each IOC consists of routing and control multiplexers, an input register/transparent latch, a three- state buffer and an output polarity control. The register/ latch can be clocked from a variety of sources determined by the global cell. It can also be bypassed for a non- registered input. The PA7572 allows the use of SUM-D as a feedback to the array when the I/O pin is a dedicated output. This allows for additional buried registers and logic paths. (See Figure 8 and Figure 9). I/O with independent output enable I/O QD Input with optional register/latch A B C D 1 2 OE DQ 08-15-008A Figure 8. LCC & IOC With Two Outputs A B C D Output 1 2 3 Buried register or logic paths QD DQ 08-15-009A Figure 9. LCC & IOC With Three Outputs Global Cells The global cells, shown in Figure 10, are used to direct global clock signals and/or control terms to the LCCs, IOCs and INCs. The global cells allow a clock to be selected from the CLK1 pin, CLK2 pin, or a product term from the logic array (PCLK). They also provide polarity control for INC and IOC clocks enabling rising or falling clock edges for input registers/latches. Note that each individual LCC clock has its own polarity control. The global cell for LCCs includes sum- of-products control terms for global reset and preset, and a fast product term control for LCC register-type, used to save product terms for loadable counters and state machines (see Figure 11). The PA7572 provides two global cells that divide the LCC and IOCs into groups, A and B. Half of the LCCs and IOCs use global cell A, half use global cell B. This means that two high-speed global clocks can be used among the LCCs. Global Cell: LCC & IOC MUX MUX CLK1 CLK2 PCLK Reg-Type Preset Reset LCC Resets LCC Presets LCC Reg-Type IOC Clocks LCC Clocks Global Cell: INC MUX CLK1 CLK2 PCLK INC Clocks Group A & B 08-15-010A Figure 10. Global Cells Register Ty pe Change Feature Global Cell can dynam ically change user- selected LCC registers from D to T or from D to JK. This saves product term s for loadable counters or state m achines. Use as D register to load, use as T or JK to count. Tim ing allow s dynam ic operation. T R P Q D R P Q Reg-Type from Glob al Cell Example: Product term s for 10 bit loadable binary counter D uses 57 product term s (47 count, 10 load) T uses 30 product term s (10 count, 20 load) D/T uses 20 product term s (10 count, 10 load) 08-15-011 A Figure 11. Register Type Change Feature |
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