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M32L1632512A
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2001
Revision : 1.6
4/54
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
VDD, VDDQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Note 1
Output high voltage
VOH
2.4
-
-
V
IOH = -2mA
Output low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
IIL
-5
-
5
µ
Â
Note 2
Output leakage current
IOL
-5
-
5
µ
Â
Note 3
Output Loading Condition
See Fig 1
Note: 1. VIL(min) = -1.5V AC (pulse width
≤ 5ns)
2. Any input 0V
≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled, 0V
≤ VOUT ≤ VDD.
CAPACITANCE (VDD/VDDQ = 3.3V, TA = 25 C
° , f = 1MHZ)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10)
CIN1
-4
pF
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE , DSF& DQM0-3)
CIN2
-4
pF
Data input/output capacitance (DQ0 ~ DQ31)
COUT
-5
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
Decoupling Capacitance between VDD & VSS
CDC1
0.1+0.01
uF
Decoupling Capacitance between VDDQ & VSSQ
CDC2
0.1+0.01
uF
*Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other.
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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