This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the

right to change or discontinue work on this proposed product without notice.

Publication Number S29JL064H

Revision A Amendment 1 Issue Date March 26, 2004

PRELIMINARY

S29JL064H

64 Megabit (8 M x 8-Bit/4 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory

Distinctive Characteristics

Architectural Advantages

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

— Zero latency between read and write operations

Flexible Bank architecture

— Read may occur in any of the three banks not being

written or erased.

— Four banks may be grouped by customer to achieve

desired bank divisions.

Boot Sectors

— Top and bottom boot sectors in the same device

— Any combination of sectors can be erased

Manufactured on 0.13 µm process technology

SecSi™ (Secured Silicon) Sector: Extra 256 Byte

sector

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function.

— Customer lockable: One-time programmable only.

Once locked, data cannot be changed

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero.

Compatible with JEDEC standards

— Pinout and software compatible with single-power-

supply flash standard

Package options

63-ball Fine Pitch BGA

48-pin TSOP

Performance Characteristics

High performance

— Access time as fast as 55 ns

— Program time: 4 µs/word typical using accelerated

programming function

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Cycling Endurance: 1 million cycles per sector

typical

Data Retention: 20 years typical

Software Features

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

— Suspends erase operations to read data from, or

program data to, a sector that is not being erased,

then resumes the erase operation.

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

Hardware Features

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin

— Write protect (WP#) function protects sectors 0, 1,

140, and 141, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

Sector protection

— Hardware method to prevent any program or erase

operation within a sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system