SLDS031A

– APRIL 1985 – REVISED APRIL 1993

4

–3

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

logic diagram (positive logic)

LATCH

ENABLE

ENABLE

OUTPUT

Buffers

Output

VCC2

R1

R2

R31

R32

Register

Shift

Latches

1D

LC32

LC31

LC2

LC1

2D

C2

2D

C2

C2

2D

2D

Q1

Q2

Q31

Q32

C2

CLOCK

DATA IN

SERIAL OUT

C1

C1

1D

C1

1D

1D

C1

28 Stages

(Q3 thru Q30)

Not Shown

FUNCTION TABLE

CONTROL INPUTS

SHIFT REGISTER

LATCHES

OUTPUTS

FUNCTION

CLOCK

LATCH

OUTPUT

SHIFT REGISTER

R1 THRU R32

LATCHES

LC1 THRU LC32

SERIAL

Q1 THRU Q32

CLOCK

ENABLE

ENABLE

R1 THRU R32

LC1 THRU LC32

SERIAL

Q1 THRU Q32

Load

No

X

X

X

X

Load and shift†

No change

Determined by

LATCH ENABLE‡

R32

R32

Determined by OUTPUT ENABLE

Latch

X

X

L

H

X

X

As determined above

Stored data

New data

R32

Determined by OUTPUT ENABLE

Output

Enable

X

X

X

X

L

H

As determined above

Determined by

LATCH ENABLE‡

R32

R32

All L

LC1 thru LC21, respectively

H = high level,

L = low level,

X = irrelevant,

= low-to-high-level transition.

† R32 and the serial output take on the state of R31, R31 takes on the state of R30,. . .R2 takes on the state of R1, and R1 takes on the state of

the data input.

‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.