CYWUSB6935 datasheet(7/33 Pages) CYPRESS

Part #	CYWUSB6935

Description	WirelessUSB LRTM 2.4-GHz DSSS Radio SoC

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CYWUSB6935

Document #: 38-16008 Rev. *C

Page 7 of 33

7.0

Register Descriptions

Table 7-1

displays the list of registers inside the

CYWUSB6935 that are addressable through the SPI interface.

All registers are read and writable, except where noted.

Note:

1.

All registers are accessed Little Endian.

Table 7-1. CYWUSB6935 Register Map[1]

Register Name

Mnemonic

CYWUSB6935

Address

Page

Default

Access

Revision ID

REG_ID

0x00

8

0x07

RO

Control

REG_CONTROL

0x03

8

0x00

RW

Data Rate

REG_DATA_RATE

0x04

9

0x00

RW

Configuration

REG_CONFIG

0x05

10

0x01

RW

SERDES Control

REG_SERDES_CTL

0x06

10

0x03

RW

Receive SERDES Interrupt Enable REG_RX_INT_EN

0x07

11

0x00

RW

Receive SERDES Interrupt Status

REG_RX_INT_STAT

0x08

12

0x00

RO

Receive SERDES Data A

REG_RX_DATA_A

0x09

13

0x00

RO

Receive SERDES Valid A

REG_RX_VALID_A

0x0A

13

0x00

RO

Receive SERDES Data B

REG_RX_DATA_B

0x0B

13

0x00

RO

Receive SERDES Valid B

REG_RX_VALID_B

0x0C

13

0x00

RO

Transmit SERDES Interrupt Enable REG_TX_INT_EN

0x0D

14

0x00

RW

Transmit SERDES Interrupt Status REG_TX_INT_STAT

0x0E

14

0x00

RO

Transmit SERDES Data

REG_TX_DATA

0x0F

15

0x00

RW

Transmit SERDES Valid

REG_TX_VALID

0x10

15

0x00

RW

PN Code

REG_PN_CODE

0x18–0x11

15

0x1E8B6A3DE0E9B222

RW

Threshold Low

REG_THRESHOLD_L

0x19

16

0x08

RW

Threshold High

REG_THRESHOLD_H

0x1A

16

0x38

RW

Wake Enable

REG_WAKE_EN

0x1C

17

0x00

RW

Wake Status

REG_WAKE_STAT

0x1D

17

0x01

RO

Analog Control

REG_ANALOG_CTL

0x20

17

0x04

RW

Channel

REG_CHANNEL

0x21

18

0x00

RW

Receive Signal Strength Indicator

REG_RSSI

0x22

18

0x00

RO

PA Bias

REG_PA

0x23

18

0x00

RW

Crystal Adjust

REG_CRYSTAL_ADJ

0x24

19

0x00

RW

VCO Calibration

REG_VCO_CAL

0x26

19

0x00

RW

Reg Power Control

REG_PWR_CTL

0x2E

20

0x00

RW

Carrier Detect

REG_CARRIER_DETECT

0x2F

20

0x00

RW

Clock Manual

REG_CLOCK_MANUAL

0x32

20

0x00

RW

Clock Enable

REG_CLOCK_ENABLE

0x33

20

0x00

RW

Synthesizer Lock Count

REG_SYN_LOCK_CNT

0x38

21

0x64

RW

Manufacturing ID

REG_MID

0x3C–0x3F

21

–

RO

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