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ICS950813YGT Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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ICS950813YGT Datasheet(HTML) 2 Page - Integrated Circuit Systems |
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2 / 22 page  2 ICS950813 Advance Information 0708—10/10/02 Pin Description PIN # PIN NAME PIN TYPE DESCRIPTION 1 VDDREF PWR Ref, XTAL power supply, nominal 3.3V 2 X1 IN Crystal input,nominally 14.318MHz. 3 X2 OUT Crystal output, Nominally 14.318MHz 4 GND PWR Ground pin. 5 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# . 6 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 7 *ASEL/PCICLK_F2 I/O Asynchronous AGP/PCI frequency latch input pin / 3.3V PCI free running clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL 8 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 9 GND PWR Ground pin. 10 PCICLK0 OUT PCI clock output. 11 **E_PCICLK1/PCICLK1 I/O Early/Normal PCI clock output latched at power up. 12 PCICLK2 OUT PCI clock output. 13 **E_PCICLK3/PCICLK3 I/O Early/Normal PCI clock output latched at power up. 14 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V 15 GND PWR Ground pin. 16 PCICLK4 OUT PCI clock output. 17 PCICLK5 OUT PCI clock output. 18 PCICLK6 OUT PCI clock output. 19 VDD3V66 PWR Power pin for the 3V66 clocks. 20 GND PWR Ground pin. 21 3V66_2 OUT 3.3V 66.66MHz clock output 22 3V66_3 OUT 3.3V 66.66MHz clock output 23 3V66_4 OUT 3.3V 66.66MHz clock output 24 3V66_5 OUT 3.3V 66.66MHz clock output 25 *PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 26 VDDA PWR 3.3V power for the PLL core. 27 GND PWR Ground pin. 28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active low input. |
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