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MCM63R918FC3.3 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MCM63R918FC3.3 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 21 page  MCM63R836 •MCM63R918 3 MOTOROLA FAST SRAM MCM63R836 PIN DESCRIPTIONS Pin Locations Symbol Type Description 4K CK Input Address, data in, and control input register clock. Active high. 4L CK Input Address, data in, and control input register clock. Active low. (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P DQx I/O Synchronous Data I/O. 4F G Input Output Enable functionality not supported. Must be tied to VSS or driven to ≤ VIL Max. 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T SA Input Synchronous Address Inputs: Registered on the rising clock edge. 5L, 5G, 3G, 3L (a), (b), (c), (d) SBx Input Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. 4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active low. 4M SW Input Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. 4U TCK Input Test Clock (JTAG). 3U TDI Input Test Data In (JTAG). 5U TDO Output Test Data Out (JTAG). 2U TMS Input Test Mode Select (JTAG). 4D ZQ Input Programmable Output Impedance: Programming pin. 7T ZZ Input Enables sleep mode, active high. 4C, 2J, 4J, 6J, 4R, 5R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply Output Power Supply: Provides operating power for output buffers. 3J, 5J Vref Supply Input Reference: Provides reference voltage for input buffers. 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R VSS Supply Ground. 4A, 1B, 2B, 4B, 7B, 1C, 7C, 4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U NC — No Connection: There is no connection to the chip. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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