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EX29BDS320-90RTCI Datasheet(PDF) 11 Page - Excel Semiconductor Inc. |
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EX29BDS320-90RTCI Datasheet(HTML) 11 Page - Excel Semiconductor Inc. |
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11 / 59 page  ES I ES I 11 Rev. 0E May 25, 2006 ES29DL320 Excel Semiconductor inc. ADVANCED INFORMATION Exit from the Security Sector Once the Security Sector is locked protected and verified, the system must write the Exit Security Sector Region command sequence to return to reading and writing the remainder of the array. Caution for the Security Sector Protection The security sector protection must be used with caution since, once protected, there is no proce- dure available for unprotecting the security sector area and none of the bits in the security sector memory space can be modified in any way. HARDWARE DATA PROTECTION The ES29DL320 device provides some protection measures against accidental erasure or program- ming caused by spurious system level signals that may exist during power transition. During power- up, all internal registers and latches in the device are cleared and the device automatically resets to the read mode. In addition, with its internal state machine built-in the device, any alteration of the memory contents or any initiation of new operation Start RESET# = VIH or VID Wait 1us Security sector Protect Verify complete Remove VIH or VID from RESET# If data=00h, security sector is unprotected. If data=01h, security sector is protected Read from security sector address with A6=0,A1=1,A0=0 Write 60h to any address Write 40h to security sector address with A6=0, A1=1,A0=0 Write reset command Figure 2. Security Sector Protect Verify can only occur after successful completion of spe- cific command sequences. And several features are incorporated to prevent inadvertent write cycles resulting from Vcc power-up and power-down transi- tion or system noise. Low Vcc Write inhibit When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc power-up and power-down. The command reg- ister and all internal program/erase circuits are dis- abled, and the device resets to the read mode. Subsequent writes are ignored until Vcc is greater than VLKO. The system must provide proper signals to the control pins to prevent unintentional writes when Vcc is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical inhibit Write cycles are inhibited by holding any one of OE#=VIL, CE#=VIH or WE#=VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-up Write Inhibit If WE#=CE#=VIL and OE#=VIH during power up, the device does not accept any commands on the rising edge of WE#. The internal state machine is automat- ically reset to the read mode on power-up. |
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