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W78ERD2A40FN Datasheet(PDF) 3 Page - Winbond

Part # W78ERD2A40FN
Description  8-BIT MICROCONTROLLER
Download  72 Pages
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Manufacturer  WINBOND [Winbond]
Direct Link  http://www.winbond.com
Logo WINBOND - Winbond

W78ERD2A40FN Datasheet(HTML) 3 Page - Winbond

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W78ERD2
Publication Release Date: April 20, 2005
- 3 -
Revision A4
1. GENERAL DESCRIPTION
The W78ERD2 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78ERD2 is fully compatible with the standard 8052. The
W78ERD2 contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM
which allows the contents of the 64KB main Flash EPROM to be updated by the loader program
located at the 4KB auxiliary Flash EPROM ROM; 256 bytes of on-chip RAM, 1K AUX-RAM; four 8-bit
bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a
serial port. These peripherals are supported by a nine sources four level interrupt capability. To
facilitate programming and verification, the Flash EPROM inside the W78ERD2 allows the program
memory to be programmed and read electronically. Once the code is confirmed, the user can protect
the code for security.
The W78ERD2 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
• 8-bit CMOS microcontroller
• Pin compatible with standard 80C52
• Instruction-set compatible with MCS-51
• Four 8-bit I/O Ports
• One extra 4-bit I/O port, interrupt, chip select function
• Three 16-bit Timers
• Programmable clock out
• Programmable Counter Array (PCA): PWM, Capture, Compare, Watchdog
• 9 interrupt sources with 4 levels of priority
• One enhanced full duplex serial port with framing error detection and automatic address
recognition
• 64KB In-system Programmable Flash EPROM (AP Flash EPRAOM)
• 4KB Auxiliary Flash EPROM for loader program (LD Flash EPROM)
• 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
• Software Reset
• 12 clocks per machine cycle operation (default). Speed up to 40 MHz.
• 6 clocks per machine cycle operation which is set by the writer. Speed up to 20 MHz.
• 2 DPTR registers
• Low EMI (inhibit ALE)
• Built-in power management with idle mode and power down mode
• Code protection
• Packages:
− DIP 40: W78ERD2A40DN
− PLCC 44: W78ERD2A40PN
− QFP 44: W78ERD2A40FN


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