CAST C2910A Megafunction Datasheet
Functional Description
The C2910A megafunction is partitioned into modules as shown above and described below.
Multiplexer
The four-input multiplexer is used to select either the register/counter, direct input, microprogram counter, or
stack as the source of the next microinstruction address.
Register Counter
This block consists of 12 D-type, edge-triggered flip-flops, with a common enable. When its load control,
RLDN is low, new data is loaded on a positive clock transition. The output of the register/counter is available
to the multiplexer as a source for the next microinstruction address. The direct input furnishes a source of
data for loading the register/counter.
Microcontroller Counter/Register (
µPC)
This block consists of a 12-bit incrementer followed by a 12-bit register. The
µPC can be used in either of two
ways: When the carry-in to the incrementer is high, the microprogram register is loaded on the next clock
cycle with the current Y output word plus one (Y + 1
→ µPC). Sequential microinstructions are thus executed.
When the carry-in is low, the incrementer passes the Y output word unmodified so that
µPC is reloaded with
the same Y word on the next clock cycle (Y
→ µPC). The same microinstruction is thus executed any number
of times.
Stack
This 9-word by 12-bit stack is used to provide return address linkage when executing microsubroutines or
loops. The stack contains a built-in stack pointer which always points to the last word written. This allows
stack reference operations (looping) to be performed without a pop.
Instruction Decoder
This block decodes the incoming instruction and generates the appropriate control signals for all the other
blocks. The instruction decoder block also generates the outputs PLN, MAPN, and VECTN
Verification Methods
The C2910A megafunction’s functionality was verified by means of a proprietary hardware modeler. The same
stimulus was applied to a hardware model which contained the original AMD 2910A chip, and the results
compared with the megafunction’s simulation outputs.
Device Utilization & Performance
Supported
Device
Utilization
Performance
Family
Tested
LEs
Memory
Memory bits
Fmax
Cyclone
EP1C20-6
294
0
0
139 MHz
Stratix
EP1S20-5
294
0
0
138 MHz
Stratix-II
EP2S60-3
232
0
0
148 MHz
CAST, Inc.
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