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M66305AP Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor |
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M66305AP Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor |
6 / 10 page 6 MITSUBISHI 〈DIGITAL ASSP〉 M66305AP/AFP TOGGLE LINE BUFFER Symbol tw ±(SIC) tw ±(SOC) tw(T) tw(RES) tw(CR1) tw(CR2) tsu(SID-SIC) th(SIC-SID) tsu(ICE-SIC) th(SIC-ICE) tsu(CS-SIC) th(SIC-CS) tsu(OCE-SOC) th(SOC-OCE) tsu(CS-SOC) th(SOC-CS) tsu(CS-T) th(T-CS) th(SIC-T) trec(T-SIC) th(SOC-T) trec(T-SOC) tsu(CS-CR1) th(CR1-CS) tsu(CS-CR2) th(CR2-CS) trec(R-SIC/SOC) trec(CR1-SIC) trec(CR2-SOC) Parameter Input clock pulse width (Note 2) Output clock pulse width (Note 2) Toggle signal input pulse width Reset input pulse width Write counter reset input pulse width Read counter reset input pulse width Input data setup time before input clock Input data hold time after input clock Input clock enable setup time before input clock Input clock enable hold time after input clock Chip select setup time before input clock Chip select hold time after input clock Output clock enable setup time before output clock Output clock enable hold time after output clock Chip select setup time before output clock Chip select hold time after output clock Chip select setup time before toggle signal input Chip select hold time after toggle signal input Toggle signal hold time after input clock Input clock recovery time after toggle signal input Toggle signal hold time after output clock Output clock recovery time after toggle signal input Chip select setup time before write counter reset Chip select hold time after write counter reset Chip select setup time before read counter reset Chip select hold time after read counter reset Input and output clock recovery time after reset Input clock recovery time after write counter reset Output clock recovery time after read counter reset TIMING CONDITIONS (Ta = –10˚C ~ 70 °C, VCC = 5V±10% and GND = 0V unless otherwise noted) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Typ. Min. 30 43* 50 150 100 100 100 25 0 25 0 150 100 25 0 150 100 100 100 100 150 100 150 100 100 100 100 100 150 150 Limits Note 2 To satisfy switching characteristic fmax = 10 MHz (frequency: 100ns), the condition shown below should be met: 100 ns ≤ (tW+) + (tW–) Symbol tc(SIC) tc(SOC) tPLH(SOC-SOD) tPHL(SOC-SOD) tPHL(SIC-BF) tPHL(SOC-INT) tPLH(T-BF) tPLH(T-INT) tPLH(R-BF) tPLH(R-INT) tPHL(CR1-BF) tPLH(CR2-INT) Parameter Input clock cycle time Output clock cycle time Propagation time between input clock and output data Propagation time between input clock and BF Propagation time between output clock and INT Propagation time between toggle signal input and BF Propagation time between toggle signal input and INT Propagation time between reset input and BF Propagation time between reset input and INT Propagation time between write counter reset and BF Propagation time between read counter reset and INT SWITCHING CHARACTERISTICS (Ta = –10˚C ~ 70 °C, VCC = 5V±10% and GND = 0V) Max. 36 40 36 40 75 85 75 85 100 100 100 100 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns Typ. Min. 100 100 Limits Test conditions CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=150pF Note 3 AC test waveform ; Input pulse level: 0V ~ 3V Input pulse rise time: 6ns *: Ta=25˚C Input pulse fall time: 6ns Test voltage ; Input voltage: 1.3V Output voltage: 1.3V |
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