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M470L3224DT0-LA0 Datasheet(PDF) 10 Page - Samsung semiconductor |
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M470L3224DT0-LA0 Datasheet(HTML) 10 Page - Samsung semiconductor |
10 / 12 page M470L3224DT0 Rev. 0.1 Jan. 2002 200pin DDR SDRAM SODIMM 8. I/O Setup/Hold Plateau Derating This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. I/O Input Level ∆tDS ∆tDH (mV) (ps) (ps) ± 280 +50 +50 Delta Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns. CK slew rate (Single ended) ∆tIH/tIS (ps) ∆tDSS/tDSH (ps) ∆tAC/tDQSCK (ps) ∆tLZ(min) (ps) ∆tHZ(max) (ps) 1.0V/ns 0 0 0 0 0 0.75V/ns +50 +50 +50 -50 +50 0.5V/ns +100 +100 +100 -100 +100 <Reference> |
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