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NCP1308DR2G Datasheet(PDF) 10 Page - ON Semiconductor

Part # NCP1308DR2G
Description  PWM Current?묺ode Controller for Free?뭃unning Quasi?뭃esonant Operation
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP1308DR2G Datasheet(HTML) 10 Page - ON Semiconductor

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NCP1308
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10
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 17.
Figure 17. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
POSSIBLE
RESTARTS
50 mV
7.0
5.0
3.0
1.0
−1.0
0 V
An internal timer prevents any restart within 10
μs
further to the driver going−low transition. This prevents the
switching frequency to exceed (1/(TON + 10
ms)) but also
avoid false leakage inductance tripping at turn−off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The NCP1308 demagnetization detection pad features a
specific component arrangement as detailed by Figure 18.
In this picture, the Zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with Rdem, a restart delay is
created and the possibility to switch right in the
drain−source wave exists. This guarantees QR operation
with all the associated benefits (low EMI, no turn−on losses
etc.). Rdem should be calculated to limit the maximum
current flowing through Pin 1 to less than +3 mA / −2 mA:
if during turn−on, the auxiliary winding delivers −30 V (at
the highest line level), then the minimum Rdem value is
defined by: (−30 + 0.7. This value will be further increased
to introduce a restart delay and also a slight filtering in case
of high leakage energy.
Figure 18. Internal Pad Implementation
TO INTERNAL
COMPARATOR
Aux
Resd
Rdem
ESD
ESD
4
1
Figure 19 portrays a typical Vds shot at nominal output
power.
Figure 19. The NCP1308 Operates in
Borderline/Critical Operation
400
300
200
100
0
Overvoltage Protection
The overvoltage works by monitoring the VCC pin via a
comparator and a reference voltage. Figure 20 portrays the
internal arrangement:
Figure 20. OVP Section Circuitry
+
50 us
FILTER
+
VCC
16 V
OVP
COMPARATOR
TO LATCH
A 50
ms time−constant filter prevents any parasitic spikes
superimposed on the VCC to adversely trigger the OVP
comparator. When the OVP comparator output goes high,
the NCP1308 fully latches off and stays latched, being
self−supplied by the DSS. The user must unplug the power
supply and wait that the VCC comes down below a reset
voltage of typically 4 V.


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