38

PS7062D

07/14/98

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PI5A381A

PI5A383A

PI5A385A

Test Circuits/Timing Diagrams

Figure 1. Switching Time

Figure 2. Charge Injection

V+

+5V

NO or

GND

NC

COM

R

GEN

1nF

V

OUT

∆V

OUT

IN

V

GEN

ON

ON

OFF

OFF

OFF

OFF

IN

Q = (

∆V

IN

Logic

Input

OFF

NC or

+3V*

+5V

IN

COM

Vcc

GND

100

15 pF

R

NO

Switch

Input

Logic

Input

L

R

L

R

L

C L

C L INCLUDES FIXTURE AND STRAY CAPACITANCE

V

OUT

(

)

+

Logic

Input

Switch

Output

50%

0V

0V

+3V

t

90%

90%

tON

t

V

r <20ns

t f <20ns

OUT

LOGIC INPUT WAVEFORMS INVERTED

FOR SWITCHES THAT HAVE OPPOSITE

LOGIC *1.5V FOR 3.3V SUPPLY