Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CY7C1372DV25-167BGXI Datasheet(PDF) 10 Page - Cypress Semiconductor

Part # CY7C1372DV25-167BGXI
Description  18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1372DV25-167BGXI Datasheet(HTML) 10 Page - Cypress Semiconductor

Back Button CY7C1372DV25-167BGXI Datasheet HTML 6Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 7Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 8Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 9Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 10Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 11Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 12Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 13Page - Cypress Semiconductor CY7C1372DV25-167BGXI Datasheet HTML 14Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 30 page
background image
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Document #: 38-05558 Rev. *A
Page 10 of 30
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
The CY7C1370DV25/CY7C1372DV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1370DV25)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
HHH
L
Write Byte b – (DQb and DQPb)L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
LHLH
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1372DV25)
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)L
H
L
Write Byte b – (DQb and DQPb)L
L
H
Write Both Bytes
L
L
L


Similar Part No. - CY7C1372DV25-167BGXI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1372DV25-167BGXI CYPRESS-CY7C1372DV25-167BGXI Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
More results

Similar Description - CY7C1372DV25-167BGXI

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1370D CYPRESS-CY7C1370D_06 Datasheet
511Kb / 28P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1370DV25 CYPRESS-CY7C1370DV25_06 Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1370D CYPRESS-CY7C1370D Datasheet
344Kb / 30P
   18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370CV25 CYPRESS-CY7C1370CV25 Datasheet
712Kb / 27P
   512K x 36/1M x 18 Pipelined SRAM with NoBL??Architecture
CY7C1370C CYPRESS-CY7C1370C Datasheet
704Kb / 27P
   512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25 CYPRESS-CY7C1372BV25 Datasheet
726Kb / 26P
   512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1460AV33 CYPRESS-CY7C1460AV33 Datasheet
395Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV25 CYPRESS-CY7C1460AV25_06 Datasheet
511Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV33 CYPRESS-CY7C1460AV33_06 Datasheet
513Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV25 CYPRESS-CY7C1460AV25 Datasheet
396Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com