4

M67025E

4146J–AERO–06/03

Functional Description

The M67025E has two ports with separate control, address and I/O pins that permit

independent read/write access to any memory location. These devices have an auto-

matic power-down feature controlled by CS. CS controls on-chip power-down circuitry

which causes the port concerned to go into stand-by mode when not selected (CS high).

When a port is selected access to the full memory array is permitted. Each port has its

own Output Enable control (OE). In read mode, the port’s OE turns the Output drivers on

when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1.

The interrupt flag (INT) allows communication between ports or systems. If the user

chooses to use the interrupt function, a memory location (mail box or message center) is

assigned to each port. The left port interrupt flag (INT

to memory location 1FFE (HEX). The left port clears the interrupt by reading address

location 1FFE. Similarly, the right port interrupt flag (INT

to memory location 1FFF (HEX), and the right port must read memory location 1FFF in

order to clear the interrupt flag (INT

defined. If the interrupt function is not used, address locations 1FFE and 1FFF are not

reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt

function.

Arbitration Logic

The arbitration logic will resolve an address match or a chip select match down to a min-

imum of 5 ns determine which port has access. In all cases, an active BUSY flag will be

set for the inhibited port.

The BUSY flags are required when both ports attempt to access the same location

simultaneously. Should this conflict arise, on-chip arbitration logic will determine which

port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that

allow the processor to hold the operation with its associated address and data. It should

be noted that the operation is invalid for the port for which BUSY is set LOW. The inhib-

ited port will be given access when BUSY goes inactive.

A conflict will occur when both left and right ports are active and the two addresses coin-

cide. The on-chip arbitration determines access in these circumstances. Two modes of

arbitration are provided: (1) if the addresses match and are valid before CS on-chip con-

trol logic arbitrates between CS

address match, on-chip control logic arbitrates between the left and right addresses for

access (refer to Table 4). The inhibited port’s BUSY flag is set and will reset when the

port granted access completes its operation in both arbitration modes.

Data Bus Width

Expansion

Expanding the data bus width to 32 or more bits in a dual-port RAM system means that

several chips may be active simultaneously. If every chips has a hardware arbitrator,

and the addresses for each arrive at the same time one chip may activate in L BUSY

signal while another activates its R BUSY signal. Both sides are now busy and the

CPUs will wait indefinitely for their port to become free.

To overcome this “Busy Lock-Out’ problem, Atmel has developed a MASTER/SLAVE

system which uses a single hardware arbitrator located on the MASTER. The SLAVE has

BUSY inputs which allow direct interface to the MASTER with no external components, giving a

speed advantage over other systems.

When dual-port RAMs are expanded in width, the SLAVE RAMs must be prevented

from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a

write cycle during a conflict situation. Conversely, the write pulse must extend a hold time

beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is

inherent in all dual-port memory systems where more than one chip is active at the same time.