MPC8540 datasheet(6/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

vi

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

1.3.14.1

RapidIO Message Unit .......................................................................................... 1-19

1.3.15

Power Management ................................................................................................... 1-19

1.3.16

Clocking..................................................................................................................... 1-20

1.3.17

Address Map .............................................................................................................. 1-20

1.3.18

OCeaN Switch Fabric ................................................................................................ 1-20

1.3.19

Processing Across the On-Chip Fabric...................................................................... 1-20

1.3.20

Data Processing with the e500 Coherency Module ................................................... 1-21

1.4

MPC8540 Application Examples .................................................................................. 1-21

1.4.1

MPC8540 Applications.............................................................................................. 1-21

Chapter 2

Memory Map

2.1

Local Memory Map Overview and Example .................................................................. 2-1

2.2

Address Translation and Mapping ................................................................................... 2-3

2.2.1

SRAM Windows .......................................................................................................... 2-4

2.2.2

Window into Configuration Space............................................................................... 2-4

2.2.3

Local Access Windows................................................................................................ 2-4

2.2.3.1

Local Access Register Memory Map ...................................................................... 2-5

2.2.3.2

Local Access Window n Base Address Registers

(LAWBAR0–LAWBAR7)................................................................................... 2-6

2.2.3.3

Local Access Window n Attributes Registers

(LAWAR0–LAWAR7)......................................................................................... 2-6

2.2.3.4

Precedence of Local Access Windows .................................................................... 2-7

2.2.3.5

Configuring Local Access Windows ....................................................................... 2-7

2.2.3.6

Distinguishing Local Access Windows from Other Mapping Functions ................ 2-8

2.2.3.7

Illegal Interaction Between Local Access Windows and DDR

SDRAM Chip Selects .......................................................................................... 2-8

2.2.4

Outbound Address Translation and Mapping Windows.............................................. 2-8

2.2.5

Inbound Address Translation and Mapping Windows ................................................ 2-9

2.2.5.1

RapidIO Inbound ATMU ......................................................................................... 2-9

2.2.5.2

PCI/PCI-X Inbound ATMU ..................................................................................... 2-9

2.2.5.3

Illegal Interaction Between Inbound ATMUs and Local Access

Windows .............................................................................................................. 2-9

2.3

Configuration, Control, and Status Register Map.......................................................... 2-10

2.3.1

Accessing CCSR Memory from External Masters .................................................... 2-11

2.3.2

Organization of CCSR Memory ................................................................................ 2-11

2.3.3

General Utilities Registers ......................................................................................... 2-13

2.3.4

Interrupt Controller and CCSR .................................................................................. 2-14

2.3.5

RapidIO and CCSR.................................................................................................... 2-15

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