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AAT2500IWP-IP-T1 Datasheet(PDF) 2 Page - Advanced Analogic Technologies |
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AAT2500IWP-IP-T1 Datasheet(HTML) 2 Page - Advanced Analogic Technologies |
2 / 26 page AAT2500 1MHz Step-Down Converter/LDO Regulator 2 2500.2006.05.1.16 Pin Descriptions Pin Configuration TDFN/STDFN33-12 (TopView) PGND LX VP 1 VCC VLDO OUT SGND FB EN ENLDO GND BYP 2 3 4 5 6 12 11 10 9 8 7 Pin # Symbol Function 1 PGND Step-down converter power ground return pin. Connect to the output and input capaci- tor return. See section on PCB layout guidelines and evaluation board layout diagram. 2 LX Power switching node. Output switching node that connects to the output inductor. 3 VP Step-down converter power stage supply voltage. Must be closely decoupled to PGND. 4 VCC Step-down converter bias supply. Connect to VP. 5 VLDO LDO input voltage; should be decoupled with 1µF or greater capacitor. 6 OUT 300mA LDO output pin. A 2.2µF or greater output low-ESR ceramic capacitor is required for stability. 7 BYP Bypass capacitor for the LDO. To improve AC ripple rejection, connect a 10nF capaci- tor to GND. This will also provide a soft-start function. 8 GND LDO ground connection pin. 9 ENLDO Enable pin for LDO. When connected low, LDO is disabled and consumes less than 1µA of current. 10 EN Step-down converter enable. When connected low, LDO is disabled and consumes less than 1µA. 11 FB Step-down converter feedback input pin. For fixed output voltage versions, this pin is connected to the converter output, forcing the converter to regulate to the specific volt- age. For adjustable output versions, an external resistive divider ties to this point and programs the output voltage to the desired value. 12 SGND Step-down converter signal ground. For external feedback, return the feedback resis- tive divider to this ground. For internal fixed version, tie to the point of load return. See section on PCB layout guidelines and evaluation board layout diagram. EP Exposed paddle (bottom). Use properly sized vias for thermal coupling to the ground plane. See section on PCB layout guidelines. |
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