Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0V, V

Internal V

mat. Typical values are for T

for T

MIN

≤ T

A

≤ T

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 9)

Units

(Limits)

Maximum Clock Frequency

155

MHz (max)

Minimum Clock Frequency

5

MHz (min)

Clock High Time

TBD

ns (min)

Clock Low Time

TBD

ns (min)

Conversion Latency

8

Clock

Cycles

Output Delay of CLK to DATA

Relative to falling edge of CLK

2.0

TBD

ns (max)

Data Output Setup Time

Relative to DRDY

2.1

1.5

ns (min)

Data Output Hold Time

Relative to DRDY

2.1

1.5

ns (min)

Aperture Delay

TBD

ns

Aperture Jitter

0.08

ps rms

Power Down Recovery Time

0.1 µF on pins 43, 44; 10 µF and 0.1 µF

between pins 43, 44; 0.1 µF and 10 µF

on pins 46, 46

3ms

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the

listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.

TBD mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to TBD.

operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such

conditions should always be avoided.

Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.

(Note 3). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.

20179011

separate bypass capacitors are used at each power supply pin.

the 14-bit LSB is 122.1 µV.

norms at the time of product characterization. The typical specifications are

not guaranteed.

Note 10: Integral Non Linearity is defined as the deviation of the analog

value, expressed in LSBs, from the straight line that passes through positive

and negative full-scale.

Note 11: The input capacitance is the sum of the package/pin capacitance

and the sample and hold circuit capacitance.

Note 12: Optimum performance will be obtained by keeping the reference

input in the 0.9V to 1.1V range. The LM4051CIM3-ADJ (SOT-23 package) is

recommended for external reference applications.

and is primarily determined by load capacitance on the output pins, the

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