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HM5117400BS-8 Datasheet(PDF) 10 Page - Hitachi Semiconductor |
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HM5117400BS-8 Datasheet(HTML) 10 Page - Hitachi Semiconductor |
10 / 25 page HM5117400B Series 10 Fast Page Mode Read-Modify-Write Cycle HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PRWC 85 — 96 — 105 — ns delay time from precharget CPW 60 — 68 — 75 — ns 14 Test Mode Cycle *19 HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Test mode setup timet WTS 0 — 0 — 0 — ns Test mode hold timet WTH 10 — 10 — 10 — ns Refresh Parameter Symbol Max Unit Note Refresh periodt REF 32 ms 2048 cycles Refresh period (L-version)t REF 128 ms 2048 cycles Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -before- refresh). If the internal refresh counter is used, a minimum of eight -before- refresh cycles are required. 3. Operation with the t RCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by t CAC. 4. Operation with the t RAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by t AA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7.V IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD t RCD (max) and tRAD t RAD (max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. |
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