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MC9S12XD256 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc

Part # MC9S12XD256
Description  16-BIT MICROPROCESSOR FAMILY
Download  28 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC9S12XD256 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc

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MC9S12XD Family, Rev. 2.14
2
Freescale Semiconductor
Features
The MC9S12XD Family will feature an enhanced MSCAN module which, when used in conjunction with
XGATE, delivers FullCAN performance with virtually unlimited number of mailboxes and retains
backwards compatibility with the MSCAN module featured on previous S12 products.
Memory options will range from 64 Kbytes to 512 Kbytes of Freescale's industry-leading, full automotive
spec SG-Flash with additional integrated EEPROM.
In addition to the rich S12 peripheral set, the MC9S12XD Family will feature more RAM, extra A/D
channels, new timer features and additional LIN-compatible SCI ports compared with the original S12 D-
Family. The MC9S12XD Family also features a new flexible interrupt handler which allows multilevel
nested interrupts.
The MC9S12XD Family has full 16-bit data paths throughout. The non-multiplexed expanded bus
interface available on the 144-pin versions allows an easy interface to external memories. The inclusion
of a PLL circuit allows power consumption and performance to be adjusted to suit operational
requirements. System power consumption is further improved with the new
“fast exit from STOP mode”
feature and an ultra low power wakeup timer.
In addition to the I/O ports available in each module, up to 25 further I/O ports are available with interrupt
capability allowing wakeup from STOP or WAIT mode.
The MC9S12XD Family will be available in 144-pin LQFP (with optional external bus), 112-pin, and 80-pin
options.
Upward compatible with MC9S12 instruction set
Enhanced indexed addressing
Additional (superset) instructions to improve 32-bit calculations and
semaphore handling
Access large data segments independent of PPAGE
Eight levels of nested interrupt
Flexible assignment of interrupt sources to each interrupt level.
One non-maskable high priority interrupt (XIRQ)
Wakeup interrupt inputs
– IRQ and non-maskable XIRQ


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