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HDD16M72D9W Datasheet(PDF) 7 Page - Hanbit Electronics Co.,Ltd |
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HDD16M72D9W Datasheet(HTML) 7 Page - Hanbit Electronics Co.,Ltd |
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7 / 11 page  HANBit HDD16M72D9W URL : www.hbe.co.kr 7 HANBit Electronics Co.,Ltd. REV 1.0 (November.2002) AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component) DDR200 DDR266A DDR266B -10A -13A -13B PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNIT NOTE Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 120K 45 120K 45 120K ns 1,2 /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 15 15 15 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD 1 1 1 tCK CL=2.0 10 12 7.5 12 10 12 ns Clock cycle time CL=2.5 tCK 12 7.5 12 7.5 12 ns Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Data out high impedence time from CK-/CK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns 2 CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns 3 DQS-in hold time tWPREH 0.25 0.25 0.25 tCK DQS-in falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS-in falling edge to CK rising hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns Power down exit time tPDEX 10 7.5 7.5 ns Exit self refresh to write command tXSW 116 95 ns Exit self refresh to bank active command tXSA 80 75 75 ns Exit self refresh to read command tXSR 200 200 200 Cycle Refresh interval time tREF 15.6 15.6 15.6 us 1 Output DQS valid window tQH - - - - - - tCK DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 4 |
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