ICS950402 datasheet(8/19 Pages) ICST

Part #	ICS950402

Description	AMD - K8 System Clock Chip

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Manufacturer	ICST [Integrated Circuit Systems]

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8

ICS950402

0700B—04/30/04

I

2C Table: Output Control Register

Control

Function

Bit 7

Reserved

RW

-

0

Bit 6

Reserved

RW

-

0

Bit 5

Reserved

RW

-

0

Bit 4

Reserved

RW

-

0

Bit 3

Reserved

RW

-

0

Bit 2

Reserved

RW

-

0

Bit 1

Reserved

RW

-

0

Bit 0

Reserved

RW

-

0

I

2C Table: Watchdog Timer Register

Control

Function

Bit 7

WD7

RW

-

0

Bit 6

WD6

RW

-

0

Bit 5

WD5

RW

-

0

Bit 4

WD4

RW

-

1

Bit 3

WD3

RW

-

0

Bit 2

WD2

RW

-

0

Bit 1

WD1

RW

-

0

Bit 0

WD0

RW

-

0

I

2C Table: VCO Control Select Bit & WD Timer Control Register

Control

Function

Bit 6

WDEN

Watchdog Enable

RW

Disable

Enable

0

Bit 7

WDRB

WD Alarm Status Bit

R

Normal

Alarm

X

Bit 4

WD SF4

RW

-

0

Bit 3

WD SF3

RW

-

0

Bit 2

WD SF2

RW

-

0

Bit 1

WD SF1

RW

-

0

Bit 0

WD SF0

RW

-

1

I

2C Table: VCO Frequency Control Register

Control

Function

Bit 7

N Div8

N Divider Bit 8

RW

-

X

Bit 6

M Div6

RW

-

X

Bit 5

M Div5

RW

-

X

Bit 4

M Div4

RW

-

X

Bit 3

M Div3

RW

-

X

Bit 2

M Div2

RW

-

X

Bit 1

M Div1

RW

-

X

Bit 0

M Div0

RW

-

X

-

The decimal

representation of M Div

(6:0) + 2 is equal to

reference divider value.

Default at power up =

latch-in or Byte 0 Rom

table.

-

RW

Disable

Byte 11

Pin #

Name

-

Type

-

Writing to these bit will

configure the safe

frequency as Byte0 bit

(5:1)

-

0

Byte 10

Pin #

Bit 7

-M/NEN

M/N Programming

Enable

Name

Type

Enable

-

These bits represent

X*290ms the watchdog

timer will wait before it

goes to alarm mode.

Default is 16 X 290ms

=4.64 seconds

-

PWD

-

Byte 8

Pin #

Name

1

Type

0

PWD

1

01

1

0

Type

Byte 9

Pin #

Name

0

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