IS42S32400B

1

PRELIMINARY INFORMATION, Rev. 00G

06/15/06

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any

time without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are

advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• Clock frequency: 166, 143, 125, 100 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Power supply

IS42S32400B

3.3V

3.3V

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Auto Refresh (CBR)

• Self Refresh with programmable refresh periods

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable

CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

• Available in Industrial Temperature

• Available in 86-pin TSOP-II and 90-ball FBGA

• Available in Lead-free

OVERVIEW

data transfer using pipeline architecture. All inputs and

outputs signals refer

to the rising edge of the clock

input.The 128Mb SDRAM is organized in 1Meg x 32 bit x 4

Banks.

4Meg x 32

128-MBIT SYNCHRONOUS DRAM

PRELIMINARY INFORMATION

JUNE 2006

KEY TIMING PARAMETERS

Parameter

-6

-7

Unit

Clk Cycle Time

CAS Latency = 3

6

7

ns

CAS Latency = 2

8

10

ns

Clk Frequency

CAS Latency = 3

166

143

Mhz

CAS Latency = 2

125

100

Mhz

Access Time from Clock

CAS Latency = 3

5.4

5.4

ns

CAS Latency = 2

6.5

6.5

ns