This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent

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Rev. 1.0 Dec 16, 2004

1/10

Features

PEEL™ 22LV10AZ-25

CMOS Programmable Electrically Erasable Logic Device

Low Voltage, Ultra Low Power Operation

- Vcc = 2.7 to 3.6 V

- Icc = 5 µA (typical) at standby

- Icc = 1.5 mA (typical) at 1 MHz

- Meets JEDEC LV Interface Spec (JESD8-A)

- 5 Volt tolerant inputs and I/O’s

CMOS Electrically Erasable Technology

- Superior factory testing

Application Versatility

General Description

The PEEL™22LV10AZ is a Programmable Electrically Erasable

Logic (PEEL™) SPLD (Simple Programmable Logic Device) that

operates over the supply voltage range of 2.7V-3.6V and fea- tures

ultra-low, automatic “zero” power-down operation. The

PEEL™22LV10AZ is logically and functionally similar to Ana-

chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The

“zero power” (50 µA max. Icc) power-down mode makes the

PEEL™22LV10AZ ideal for a broad range of battery-powered

portable equipment applications, from hand-held meters to PCM-

CIA modems. EE-reprogrammability provides both the conve-

nience of fast reprogramming for product development and quick

product personalization in manufacturing, including Engineering

Change Orders.

Figure 26 Pin Configuration

Architectural Flexibility

Schmitt Trigger Inputs

- Ideal for encoder designs

The

differences

between

the

PEEL™22LV10AZ

and

PEEL™22CV10A include the addition of programmable clock

polarity, p-term clock, and Schmitt trigger input buffers on all

inputs, including the clock. Schmitt trigger inputs allow direct

input of slow signals such as biomedical and sine waves or

clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin

and JEDEC compatible, logical superset of the industry stan- dard

PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides

additional architectural features that allow more logic to be

incorporated into the design. The PEEL™22LV10AZ architec-

ture allows it to replace over twenty standard 24-pin DIP, SOIC,

TSSOP and PLCC packages.

Figure 26 Block Diagram

I/CLK

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

GND

12

24

VCC

23

I/O

22

I/O

21

I/O

20

I/O

™

19

I/O

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I

DIP

TSSOP

PLCC

SOIC