CY2SSTU877LFXC-XX datasheet(4/9 Pages) CYPRESS

Part #	CY2SSTU877LFXC-XX

Description	1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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4 / 9 page

PRELIMINARY

CY2SSTU877

Document #: 38-07575 Rev. *B

Page 4 of 9

Tjit (H-Period)

Half Period Cycle-to-cycle jitter

Above 270 MHz

–45

45

ps

Below 270 MHz

–70

70

ps

Td(0)

Static Phase Offset

Average 1000 cycles

–50

50

ps

Td(0)

Dynamic Phase Offset

–30

30

ps

TSKEW

Clock Skew

–

25

ps

TR/TF

Rise/Fall Time

(Y[0:9], Y#[0:9] @ 500 MHz)

–

300

ps

TODC

Output Duty Cycle

49

51

%

TOENB

Output Enable Time

OE to any Y/Y#

–

8

ns

TODIS

Output Disable Time

OE to any Y/Y#

–

8

ns

TPLH

Propagation Delay

8

ns

AC Timing Specifications (continued)

Parameter

Description

Conditions

Min.

Max.

Unit

Figure 1. Test Loads for Timing Measurement #1

Figure 2. Test Loads for Timing Measurement #2

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