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AWT6307R Datasheet(PDF) 1 Page - ANADIGICS, Inc

Part # AWT6307R
Description  HELP Cellular CDMA 3.4 V/28 dBm Linear Power Amplifier Mod
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Manufacturer  ANADIGICS [ANADIGICS, Inc]
Direct Link  http://www.anadigics.com
Logo ANADIGICS - ANADIGICS, Inc

AWT6307R Datasheet(HTML) 1 Page - ANADIGICS, Inc

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03/2006
AWT6307R
HELPTM Cellular CDMA 3.4 V/28 dBm
Linear PowerAmplifier Module
PRELIMINARY DATA SHEET - Rev 1.0
M9 Package
8 Pin 3 mm x 3 mm x 1 mm
Surface Mount Module
FEATURES
InGaP HBT Technology
High Efficiency:
21 % @ +16 dBm output
40 % @ +28 dBm output
Low Quiescent Current: 16 mA
Low Leakage Current in Shutdown Mode: <1
µA
Internal Voltage Regulation
Optimized for a 50
Ω System
Low Profile Surface Mount Package: 1 mm
CDMA 1XRTT, 1xEV-DO Compliant
Pinout Enables Easy Phone Board Migration
From 4 mm x 4 mm Package
RoHS Compliant Package, 250 oC MSL-3
APPLICATIONS
CDMA Wireless Handsets and Data Devices
PRODUCT DESCRIPTION
The AWT6307R meets the increasing demands for
higher efficiency and smaller footprint in CDMA 1X
handsets. The package pinout was chosen to
enable handset manufacturers to switch from a
4 mm x 4 mm PA module with few layout changes
while reducing board area requirements by 44 %.
The AWT6307R uses ANADIGICS’ exclusive InGaP-
Plus™ technology, which combines HBT and
pHEMT devices on the same die, to enable state-
of-the-art reliability, temperature stability, and
ruggedness. The AWT6307R is part of ANADIGICS’
High-Efficiency-at-Low-Power (HELP™) family of
CDMA power amplifiers, which deliver low quiescent
currents and significantly greater efficiency without
a costly external DAC or DC-DC converter. Through
selectable bias modes, the AWT6307 achieves
optimal efficiency across different output power
levels, specifically at low- and mid-range power
levels where the PA typically operates, thereby
dramatically increasing handset talk-time and
standby-time. Its built-in voltage regulator eliminates
the
need
for
external
voltage
regulation
components. The 3 mm x 3 mm x 1 mm surface
mount package incorporates matching networks
optimized for output power, efficiency and linearity
in a 50
Ω system.
Figure 1: Block Diagram
AW
T6307R
AW
T630
7R
Bias Control
VBATT
VEN
RFIN
RFOUT
GND
VMODE
1
7
8
6
GND at slug (pad)
3
4
2
VCC
GND
5


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