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APW702612KC-TR Datasheet(PDF) 4 Page - Anpec Electronics Coropration |
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APW702612KC-TR Datasheet(HTML) 4 Page - Anpec Electronics Coropration |
4 / 11 page Copyright ANPEC Electronics Corp. Rev. A.2 - Sep., 2001 APW7026 www.anpec.com.tw 4 Electrical Characteristics Cont. Functional Pin Description 1. Recommended operating conditions, Unless otherwise noted. 2. Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic. AP W 7 0 2 6 U n i t S y m b ol P a r a m e t e r T e s t C ondi t i ons Mi n T y p Ma x PR O T EC T I O N V S E N 1 O . V . t r i p poi nt ( V S E N 1 / V RE F 1 ) VS EN 1 R i s i n g 11 8 % V S E N 1 O . V . H y s t er es i s 2% V 3 . 3 O . V . t r i p po i n t V 3. 3 R i s i ng 4. 1 V V 3 . 3 O . V . H y s t er es i s 0. 1 V l OV P F A U L T S o ur i n g C u r r e n t V FA U LT /R T = 2. 0V 25 m A O C S E T 1, 2 C u r r e n t S o ur c e V o c s e t = 4. 5V 170 200 230 uA R SS P u l l u p r e si st o r t o 5 V 23 K Ω P O W E R GOOD VS EN 1 U p p e r T h r e s h o l d (V S E N 1 / V RE F 1 ) VS EN 1 R i s i n g 1 1 0 % V S E N 1 Low er T h r e s h o l d V S E N 1 R i s i ng 94 % V S E N 1 P G D H y s t er esi s U pper / L ow er T h r e s h o l d 2 % V 3 . 3 Low er T h r e s h o l d V 3. 3 R i s i ng 2. 5 V V3 . 3 PG D H y s t e r e s i s 0. 1 V FB 3 L o w e r Th r e s h o l d V FB3 R i s i ng 1. 0 V F B 3 P G D H y s t er es i s 0. 1 V V P GOOD P G OOD V o l t a g e L o w l P GOOD = - 4 m A 0 . 8 V UGATE1 (Pin 1) Connect UGATE1 pin to the SYNC PWM Converter’s upper MOSFET gate .This pin provides the gate drive for the upper MOSFET. VCC (Pin 2) Provide a + 12V bias supply for the IC to this pin . This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purpose. UGATE2 (Pin 3) Connect UGATE2 pin to the ASYNC PWM converter’s MOSFET gate . This pin provides the gate drive for the MOSFET. PHASE2 (Pin 4) Connect the PHASE2 pin to the ASYNC PWM converter’s MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. PGOOD (Pin 5) PGOOD is an open drain output used to indicate the status of the output voltages. This pin is pulled low when the SYNC PWM regulator output is not within ± 10% of the reference voltage (V REF1) or when V3.3 or V FB3 is below its lower power good threshold. OCSET2 (Pin 6) Connect a resistor (R OCSET ) from this pin to the drain of the ASYNC PWM converter’s MOSFET . R OCSET, an internal 200 µA current source (I OCSET ) , and the MOSFET’s on-resistance (r DS(ON)) set the converter’s over-current (OC) trip point according to the following equation: I PEAK = An over-current trip cycles the soft-start function. FB2 (Pin 7) Connect this pin to the output of the ASYNC PWM converter . The voltage at this pin is regulated to the reference voltage V REF2 . A resistor driver is connected from this pin to V OUT2(ROUT2) and to GND(RGND2) that sets the output voltage as the following equation : I OCSET x ROCSET r DS(ON) |
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