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APW7068KE-TUL Datasheet(PDF) 5 Page - Anpec Electronics Coropration |
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APW7068KE-TUL Datasheet(HTML) 5 Page - Anpec Electronics Coropration |
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5 / 26 page  Copyright © ANPEC Electronics Corp. Rev. A.2 - Jun., 2006 APW7068 www.anpec.com.tw 5 Unless otherwise specified, these specifications apply over VCC12=12V, and TA =-20~70 °C. Typical values are at T A=25°C. Electrical Characteristics (Cont.) APW7068 Symbol Parameter Test Conditions Min Typ Max Unit REFERENCE VREF Reference Voltage for Error Amp1 and Amp2 0.792 0.80 0.808 V Reference Voltage Tolerance -1 +1 % PWM Load Regulation IOUT1=0 to 10A 1 % Linear Load Regulation IOUT2=0 to 3A 1 % PWM ERROR AMPLIFIER Gain Open Loop Gain RL=10k, CL=10pF (NOTE3) 93 dB GBWP Open Loop Bandwidth RL=10k, CL=10pF (NOTE3) 20 MHz SR Slew Rate RL=10k, CL=10pF (NOTE3) 8 V/us FB Input Current VFB=0.8V 0.1 1 uA VCOMP COMP High Voltage 5 V VCOMP COMP Low Voltage 0 V ICOMP COMP Source Current COMP=2V 12 mA ICOMP COMP Sink Current COMP=2V 12 mA GATE DRIVERS IUGATE Upper Gate Source Current 2.5 A IUGATE Upper Gate Sink Current BOOT=12V, UGATE-PHASE = 2V 2 A ILGATE Lower Gate Source Current 2.5 A ILGATE Lower Gate Sink Current VCC12=12V, LGATE=2V 3.5 A RUGATE Upper Gate Source Impedance BOOT=12V, IUGATE=0.1A 2.25 3.375 Ω RUGATE Upper Gate Sink Impedance BOOT=12V, IUGATE=0.1A 0.7 1.05 Ω RLGATE Lower Gate Source Impedance VCC12=12V, ILGATE=0.1A 2.25 3.375 Ω RLGATE Lower Gate Sink Impedance VCC12=12V, ILGATE=0.1A 0.4 0.6 Ω TD Dead Time 20 nS LINEAR REGULATOR Gain Open Loop Gain RL=10k, CL=10pF (NOTE3) 70 dB GBWP Open Loop Bandwidth RL=10k, CL=10pF (NOTE3) 19 MHz SR Slew Rate RL=10k, CL=10pF (NOTE3) 6 V/us FBL Input Current VFBL=0.8V 0.1 1 uA VDRIVE DRIVE High Voltage 10 V VDRIVE DRIVE Low Voltage 0 V IDRIVE DRIVE Source Current DRIVE=5V 4 mA IDRIVE DRIVE Sink Current DRIVE=5V 3 mA |
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