2

COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

NC

NC

GND

GND

GND

NC

NC

GND

GND

GND

GND

NC

NC

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

4658 drw 02

DESCRIPTION (CONTINUED)

NOTES:

1. NC – No internal connection.

2. Uses Yamaichi socket IC51-1324-828.

PIN CONFIGURATION

*

PQFP (PQ132-1, order code: PQF)

TOP VIEW

two 36-bit mailbox registers. Each mailbox register has a flag to signal when

newmailhasbeenstored. Twoormoredevicesmaybeusedinparalleltocreate

wider data paths. Expansion is also possible in word depth.

These devices are a clocked FIFO, which means each port employs a

synchronous interface. All data transfers through a port are gated to the LOW-

to-HIGH transition of a continuous (free-running) port clock by enable signals.

The continuous clocks for each port are independent of one another and can

be asynchronous or coincident. The enables for each port are arranged to

provide a simple interface between microprocessors and/or buses with

synchronous control.

TheInputReady(IR)flagandAlmost-Full(

AF)flagoftheFIFOaretwo-stage

synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (

AE)

flag of the FIFO are two-stage synchronized to CLKB. Offset values for the

Almost-FullandAlmost-EmptyflagsoftheFIFOcanbeprogrammedfromport

A or through a serial input.

The IDT72V3631/72V3641/72V3651 are characterized for operation from

0

°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by

specialorder. ThesedevicesarefabricatedusingIDT'shighspeed,submicron

CMOS technology.