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COMMERCIALTEMPERATURERANGE

IDT72V3631/72V3641/72V3651

3.3V CMOS SYNCFIFO™ 512 x 36, 1,024 x 36 and 2,048 x 36

PIN DESCRIPTION

Symbol

Name

I/O

Description

A0-A35

Port-A Data

I/O 36-bit bidirectional data port for side A.

AE

Almost-Empty

O

Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to

Flag

the value in the Almost-Empty register (X).

AF

Almost-Full

O

Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or

Flag

equal to the value in the Almost-Full Offset register (Y).

B0-B35

Port-B Data

I/O 36-bit bidirectional data port for side B.

CLKA

Port-A Clock

I

CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or

coincident to CLKB. IR and

AF are synchronous to the LOW-to-HIGH transition of CLKA.

CLKB

Port-B Clock

I

CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or

coincident to CLKA. OR and

AE are synchronous to the LOW-to-HIGH transition of CLKB.

CSA

Port-A Chip

I

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35

Select

outputs are in the high-impedance state when

CSA is HIGH.

CSB

Port-B Chip

I

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35

Select

outputs are in the high-impedance state when

CSB is HIGH.

ENA

Port-A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.

ENB

Port-B Enable

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.

FS1/

Flag-Offset

I

FS1/

SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset,

SEN,

Select 1/

FS1/

SENandFS0/SDselectstheflagoffsetprogrammingmethod.ThreeOffsetregisterprogrammingmethodsare

Serial Enable

available: automatically load one of two preset values, parallel load from port A, and serial load.

FS0/SD

Flag Offset 0/

When serial load is selected for flag Offset register programming, FS1/

SEN is used as an enable synchronous to

Serial Data

the LOW-to-HIGH transition of CLKA. When FS1/

SEN is LOW, a rising edge on CLKA load the bit present on FS0/

SD into the X and Y registers. The number of bit writes required to program the Offset registers is 18/20/22 for the

IDT72V3631/72V3641/72V3651 respectively. The first bit write stores the Y-register MSB and the last bit write stores

the X-register LSB.

IR

Input Ready

O

IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its

Flag

array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point

of the retransmit data and prevents further writes. IR is set LOW during reset and is set HIGH after reset.

MBA

Port-A Mailbox

I

A HIGH level chooses a mailbox register for a port-A read or write operation.

Select

MBB

Port-B Mailbox

I

A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active,

Select

a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output.

MBF1

Mail1 Register

O

MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH

Flag

by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH.

MBF1 is set HIGH by a

reset.

MBF2

Mail2 Register

O

MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH

Flag

by a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH.

MBF2 is set HIGH by a

reset.

OR

Output Ready

O

OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are

Flag

disabled. Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the

reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.

RFM

Read From

I

When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read

Mark

pointer to the beginning retransmit location and output the first selected retransmit data.

RST

Reset

I

To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur

while

RST is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset

selection.

RTM

Retransmit

I

When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition

Mode

of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word

remains the initial retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO

out of retransmit mode.

W/

RA

Port-AWrite/

I

A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of

Read Select

CLKA. The A0-A35 outputs are in the high-impedance state when W/

RA is HIGH.

W/RB

Port-BWrite/

I

A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of

Read Select

CLKB. The B0-B35 outputs are in the high-impedance state when

W/RB is LOW.