HANBit

HFDOM40MVxxx

URL:www.hbe.co.kr

10 / 10

HANBit Electronics Co., Ltd.

Rev. 1.0 (January. 2004)

Bit 5: This bit is set to 1.

Bit 4 (DRV): DRV is the drive number. When DRV=0, drive (card) 0 is selected. When DRV=1, drive (card)

1 is selected. The CompactFlash Storage Card is set to be Card 0 or 1 using the copy field

(Drive #) of the PCMCIA Socket & Copy configuration register.

Bit 3 (HS3): When operating in the Cylinder , Head, Sector mode, this is bit 3 of the head number. It is Bit

27 in the Logical Block Address mode.

Bit 2 (HS2): When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is Bit

26 in the Logical Block Address mode.

Bit 1 (HS1): When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit

25 in the Logical Block Address mode.

Bit 0 (HS0): When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit

24 in the Logical Block Address mode.

Status & Alternate Status Register

These registers return the CompactFlash Storage Card status when read by the host. Reading the Status

register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits

are described as follows:

D7

D6

D5

D4

D3

D2

D1

D0

BUSY

RDY

DWF

DSC

DRQ

CORR

0

ERR

Bit 7 (BUSY): The busy bit is set when the CompactFlash Storage Card has access to the command buffer

and registers and the host is locked out from accessing the command register and buffer. No

other bits in this register are valid when this bit is set to a 1.

Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card

operations. This bit is cleared at power up and remains cleared until the CompactFlash

Storage Card is ready to accept a command.

Bit 5 (DWF): This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready.

Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be

transferred either to or from the host through the Data register.

Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been

corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX): This bit is always set to 0.

Bit 0 (ERR): This bit is set when the previous command has terminated with some type of error. The bits in

the Error register contain additional information describing the error. It is recommended that

media access commands (such as Read Sectors and Write Sectors) that end with an error

condition should have the address of the first sector in error in the command block registers.

Device Control Register

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft

reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

1

SW Rst

-IEn

0

Bit 7: This bit is an X (don’t care).

Bit 6: This bit is an X (don’t care).

Bit 5: This bit is an X (don’t care).

Bit 4: This bit is an X (don’t care).

Bit 3: This bit is ignored by the CompactFlash Storage Card.

Bit 2 (SW Rst): This bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk

controller Soft Reset operation. This does not change the PCMCIA Card Configuration

Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains Reset until this bit

is reset to ‘0.’

Bit 1 (-IEn): The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from

the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the

Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0: This bit is ignored by the CompactFlash Storage Card.